AEM Holdings - Maybank Kim Eng 2019-06-18: System Level Test – At An Inflection Point


AEM Holdings - System Level Test – At An Inflection Point

At the right place, at the right time

  • 5G is expected to usher greater levels of device interconnectivity. Chips are also increasingly complex and mission-critical. To test chips efficiently and effectively, chipmakers are increasingly looking to system level test (SLT) to complement conventional methods. AEM Holdings (SGX:AWX) appears well positioned given its early mover advantage and strong know-how.
  • AEM may even be an attractive M&A target, given attractive valuation of 6x FY19E EV/EBITDA.
  • ROE-g/COE-g Target Price of SGD1.40 for AEM, based on 3.1x FY19E P/B is unchanged. BUY.

System level test is reaching an inflection point

  • As 5G enables the widespread adoption of many emerging technologies like massive IoT and autonomous driving, we expect the continuation of two trends –
    1. chips will be increasingly complex, e.g. from the emergence of new packaging technologies; and
    2. chips will be increasingly mission critical, e.g. failure in an automotive chip can result in passenger injury or death, massive recalls, lawsuits, and potentially irreparable reputational damage.
  • In addition, some of these emerging technologies require increasingly stringent reliability. For instance, some automotive chips have to endure extreme hot/cold temperatures and still last for 10-15 years.
  • On the back of such trends, the shortfalls of conventional test methods, i.e. structural and functional test are rising. This is because unlike system level test, which integrates as much software and hardware to mimic real world scenarios as possible, functional test merely checks if the chip functions per its hardware design, based on vectors determined by engineers. As such, SLT’s key advantage over functional test is SLT’s ability to capture faults that functional tests may not.
  • For better understanding of SLT’s advantages over conventional test methods, we illustrate four current trends:

Conventional method is increasingly inadequate at newer nodes -

  • Moore’s law states that the number of transistors doubles with each new technology node. According to Astronics Test Systems (ATS), the coverage percentage under conventional methods (i.e. ATE + design for test) has been unchanged at 99.5%. This can result in an unacceptable level of untested transistors, because as this number gets higher, the greater the risk of test escapes. At the 22nm node, based on a 2.5b transistor IC, a 99.5% coverage results in 12.5m untested transistors. However, at the 7nm node (20b transistor IC), the number of untested transistors is 100m.
  • With increasing numbers of untested transistors, risks of defective units escaping detection rise. As SLT tests the device-under-test (DUT) in a final product environment and production, it is able to complement structural and functional tests to yield maximum test coverage.

Concurrent scenarios result in complex test scenarios -

  • Leading-edge electronic devices (e.g. mobile phones, autonomous vehicles) can handle multiple applications simultaneously. This is referred to as “concurrent scenarios.” Developing test patterns for every real-world scenario under the conventional method is extremely difficult.
  • For instance, there is an extremely large permutation of the number and combination of apps that a smartphone can run simultaneously. Sometimes, concurrent scenarios involve mission critical and safety critical outcomes, such as passenger safety in an autonomous vehicle. During such instances, such as when a self-driving vehicle which is running many applications simultaneously (e.g. using GPS, receiving calls, etc.), the vehicle must prioritise navigating itself safely and the safety of its passengers over other applications. SLT, by mimicking real world situations, is able to test for such scenarios effectively.

Complex devices require new test paradigms.

  • SLT is able to catch faults stemming from new packaging technologies and increased device complexities, which conventional methods of structural and functional test are not able to. For instance, with a system in package (SiP) device, even if test results from conventional methods show a 100% yield for each IP, combining the different IP into a single package may not guarantee 100% coverage.
  • Meanwhile, CPUs and application processors that handle emerging applications such as AI that require high I/Os to process large amounts of data have increased potential for latency-related defects. With rising demands and complexity of devices, SLT can be a cost-effective method of providing additional fault coverage on top of conventional methods.
  • Based on the trajectory of these trends, the adoption of system level test among chipmakers may be reaching an inflection point, in our view. While the concept of SLT is not new, Semiconductor Engineering, a semiconductor insights website targeted at professionals, highlights that adoption has so far been only amongst large semiconductors.

Understanding the adoption hurdles

  • We believe still nascent adoption can be attributed to two main hurdles. The first is that SLT represents a huge paradigm shift in the way chipmakers currently test their chips. In a conventional approach, the test environment can be set up and determined at the chip manufacturing stage. However, SLT requires that the test strategy (i.e. what aspects and how a chip is tested, and when these aspects are tested) be well-considered at the chip design stage. This necessitates that chipmakers weigh the benefits of SLT against the cost of implementation (e.g. upfront cost of chip design, new SLT equipment, total cost of test, etc).
  • Due to this hurdle, we expect full customer conversion to adopt system level test can take 2-3 years, as time is needed for the customer’s education and R&D to adapt for SLT (e.g. changes to chip design), as well as prototyping and commercial ramp-up for the SLT test equipment.
  • The second hurdle is whether a chipmaker’s CoT will reduce upon adopting SLT. According to Astronics Test Systems, SLT test durations could be longer than conventional methods, if chips are tested on ATE or low parallelism SLT testers. This is because time to boot, loading the operating system, and shut down have to be factored in under SLT. In order to lower the CoT, SLT systems should be massively parallel and asynchronous to increase throughput. We note that AEM’s SLT solutions are asynchronous and massively parallel.

AEM is favourably positioned

  • We believe AEM is uniquely positioned to capture opportunities from rising interest in SLT. On one hand, we expect AEM’s positive relationship with the customer to be robust as HDMT continues to be rolled-out within the customer. On the other, we believe AEM’s success with its main customer may be a strong reference point for potential customer wins for its new SLT test handling system – AMPS (asynchronous, modular, parallel, smart).
  • We believe the following observations corroborate this view:
    1. AEM has a longstanding relationship with its customer, a pioneer in SLT – AEM has been supporting its key customer’s SLT solutions since the early 2000s. With HDMT – which underwent mass production in 2017, AEM’s customer claims that it has achieved 2x its intended cost savings, and now boasts among the lowest CoT in the industry. Prior to HDMT, AEM’s SLT handler was called STHI, which it sold since 2002.
    2. Many factors driving stickiness with key customer – Given HDMT’s accomplishments in driving lowered CoT, AEM believes future chips from this customer will be mostly designed to be tested using HDMT. AEM owns the patent and is the sole source for the HDMT test handler, an essential component of the HDMT framework. In addition, AEM is able to meet its customer’s stringent requirements in engineering and global field service support. It is able to copy exactly its manufacturing requirements. While the risk of HDMT being replaced by a competitor’s platform cannot be ruled out, we believe this will take several years, given lead times required for product R&D, and for the launch of new chips to be tested on the competitor’s platform thereafter.
    3. AEM’s SLT systems yield high throughput to lower CoT - With HDMT and AMPS, AEM is able to consolidate multiple test processes (i.e. burn-in, functional, and SLT) into a single test process. AEM’s solutions are also massively parallel and asynchronous, which boosts throughput. As AEM provides a single platform that supports development, validation and mass production, this boosts the customer’s ability to improve production scalability and time to market. As with HDMT, AEM says that AMPS will be highly customised for each chipmaker customer, as the test requirements of no two chipmakers are the same. We believe this represents a compelling proposition for potential customers.

Competitive landscape heating up

  • As SLT gains interest among chipmakers, competition has been heating up. We believe this implies AEM has to be more aggressive in business development efforts. In our view, the impact to our FY19-20E forecasts, if any, would be from higher than expected staff costs, as AEM might hire additional engineering, marketing, and strategic product development talent. We do not see a negative impact to our FY19-20E revenue forecasts from rising competitive dynamics as we have not factored in AMPS customer wins beyond the memory customer that AEM secured in 2018.
  • We believe the primary source of intensifying competition stems from Advantest’s (6857 JP) recent acquisition of Astronics’ semiconductor test business (AST), as:
    1. Horizontal integration – The acquisition brings AST’s SLT capabilities, highly complementary to Advantest’s domain expertise in test equipment, under one roof. This contrasts AEM’s solutions, which presently relies on testers manufactured by other equipment companies.
    2. AST will have access to Advantest’s global customer base and depth of resource. This transaction helps ATS overcome prior challenges of scaling customer base without extraordinary levels of investment. Contrastingly, AEM is building new customer relationships from scratch.
    3. AST’s SLT framework is also asynchronous and massively parallel, similar to AEM’s solutions. ATS claims its SLT platform is able to test up to 396 devices simultaneously, while we understand through channel checks that HDMT’s parallelism is up to 120 devices.
  • Notwithstanding, we believe a mitigation factor is that Advantest may cap the growth of AST, to avoid AST cannibalising the lucrative prospects of the Advantest’s existing ATE business. Aside from Advantest, we gather that Teradyne (TER US) and Cohu (COHU US) have also launched their system level test solutions, the Titan and Solstice respectively.

A potential M&A candidate

  • Given AEM’s track record in SLT, we believe it may be an interesting M&A target, as:
    1. Solid track record in SLT – AEM has supplied its key customer with SLT solutions since 2002. AEM has benefitted by learning industry-leading know-how along the way.
    2. Merger synergies – An acquirer with a global clientele could unlock new customers for AEM. Meanwhile, horizontal integration with a tester company could also unlock product synergies.
    3. Attractive valuation – AEM is currently trading at 6x FY19E EV/EBITDA. This compares favourably to the 7-8x EV/EBITDA that Cohu acquired Xcerra for, and the median of 10x based on comparable transactions in recent years.
  • However, we understand that while AEM is open to M&A conversations, it is not actively searching for a suitor.
  • See AEM Holdings Share Price; AEM Holdings Target Price; AEM Holdings Analyst Reports; AEM Holdings Dividend History; AEM Holdings Announcements; AEM Holdings Latest News.

Gene Lih Lai CFA Maybank Kim Eng Research | https://www.maybank-ke.com.sg/ 2020-06-18
SGX Stock Analyst Report BUY MAINTAIN BUY 4.040 SAME 4.040